Table of Contents
(NOTE: Each chapter concludes with a Summary and Exercises.)
About the Author.
Foreword.
Preface.
Acknowledgments.
I. BASIC VERILOG TOPICS.
1. Overview of Digital Design with Verilog HDL.
Evolution of Computer-Aided Digital Design. Emergence of HDLs.
Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL.
Trends in HDLs.
2. Hierarchical Modeling Concepts.
Design Methodologies. 4-bit Ripple Carry Counter. Modules.
Instances. Components of a Simulation. Example.
3. Basic
Concepts.
Lexical Conventions. Data Types. System Tasks and Compiler
Directives.
4. Modules and Ports.
Modules. Ports. Hierarchical Names.
5. Gate-Level
Modeling.
Gate Types. Gate Delays.
6. Dataflow Modeling.
Continuous Assignments. Delays. Expressions, Operators, and
Operands. Operator Types. Examples.
7. Behavioral
Modeling.
Structured Procedures. Procedural Assignments. Timing Controls.
Conditional Statements. Multiway Branching. Loops. Sequential and
Parallel Blocks. Generate Blocks. Examples.
8. Tasks and
Functions.
Difference between Tasks and Functions. Tasks. Functions.
9.
Useful Modeling Techniques.
Procedural Continuous Assignments. Overriding Parameters.
Conditional Compilation and Execution. Time Scales. Useful System
Tasks.
II. ADVANCED VERILOG TOPICS.
10. Timing and Delays.
Types of Delay Models. Path Delay Modeling. Timing Checks. Delay
Back-Annotation.
11. Switch Level Modeling.
Switching-Modeling Elements. Examples.
12. User-Defined
Primitives.
UDP basics. Combinational UDPs. Sequential UDPs. UDP Table
Shorthand Symbols. Guidelines for UDP Design.
13. Programming
Language Interface.
Uses of PLI. Linking and Invocation of PLI Tasks. Internal Data
Representation. PLI Library Routines.
14. Logic Synthesis with
Verilog HDL.
What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL
Synthesis. Synthesis Design Flow. Verification of the Gate-Level
Netlist. Modeling Tips for Logic Synthesis. Example of Sequential
Circuit Synthesis.
15. Advanced Verification Techniques.
Traditional Verification Flow. Assertion Checking. Formal
Verification.
III. APPENDICES.
Appendix A. Strength Modeling and Advanced Net
Definitions.
Strength Levels. Signal Contention. Advanced Net Types.
Appendix
B. List of PLI Routines.
Conventions. Access Routines. Utility (tf_) Routines.
Appendix C.
List of Keywords, System Tasks and Compiler Directives.
Keywords. System Tasks and Functions. Compiler
Directives.
Appendix D. Formal Syntax Definition.
Source Text. Declarations. Primitive Instances. Module and
Generated Instantiation. UDP Declaration and Instantiation.
Behavioral Statements. Specify Section. Expressions.
General.
Appendix E. Verilog Tidbits.
Appendix F. Verilog Examples.
Synthesizable FIFO Model. Behavioral DRAW
Model.
Bibliography.
Index.Promotional Information
Verilog HDL is a language for digital design, just as C is a
language for programming. This complete Verilog HDL reference
progresses from the basic Verilog concepts to the most advanced
concepts in digital design. Palnitkar covers the gamut of Verilog
HDL fundamentals, such as gate, RTL, and behavioral modeling, all
the way to advanced concepts, such as timing simulation, switch
level modeling, PLI, and logic synthesis. Verilog HDL is a hardware
description language (with a user community of more than 50,000
active designers) used to design and document electronic systems.
This completely updated reference progresses from basic to advanced
concepts in digital design, including timing simulation, switch
level modeling, PLI, and logic synthesis.
About the Author
About the Author Samir Palnitkar is a recognized authority on
Verilog HDL, modeling, verification, logic synthesis, and EDA-based
methodologies in digital design. He has worked extensively with
design and verification on various successful microprocessor, ASIC,
and system projects. He was the lead developer of the Verilog
framework for the shared memory, cache coherent, multiprocessor
architecture, popularly known as the UltraSPARCTM Port
Architecture, defined for Sun's next generation UltraSPARC-based
desktop systems. Besides the UltraSPARC CPU, he has worked on a
number of diverse design and verification projects at leading
companies including Cisco, Philips, Mitsubishi, Motorola, National,
Advanced Micro Devices, and Standard Microsystems.