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CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom


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Table of Contents

List of Abbreviations. Preface. CHAPTER 1 - SD ADCs: Principles, Architectures, and State of the Art. 1.1. Analog-to-Digital Conversion: Fundamentals. 1.2. Oversampling SD ADCs: Fundamentals. 1.3. Single-Loop SD Architectures. 1.4. Cascade SD Architectures. 1.5. Multi-Bit SD Architectures. 1.6. Parallel SD Architectures. 1.7. State of the Art in SD ADCs. 1.8. Summary. CHAPTER 2 - Non-Ideal Performance of SD Modulators. 2.1. Integrator Leakage. 2.1.1. Single-loop SD modulators. 2.1.2. Cascade SD modulators. 2.2. Capacitor Mismatch. 2.3. Integrator Settling Error. 2.4. Circuit Noise. 2.5. Clock Jitter. 2.6. Sources of Distortion. 2.7. Summary. CHAPTER 3 - A Wideband SD Modulator in 3.3-V 0.35-um CMOS. 3.1. Design Methodology. 3.2. Topology Selection. 3.3. Switched-Capacitor Implementation. 3.4. Specifications for the Building Blocks. 3.5. Design of the Building Blocks. 3.6. Layout and Prototyping. 3.7. Experimental Results. 3.8. Performance Summary. 3.9. Performance Comparison with the State of the Art. 3.10. Summary. CHAPTER 4 - A SD Modulator in 2.5-V 0.25-um CMOS for ADSL/ADSL+. 4.1. Topology Selection. 4.2. Switched-Capacitor Implementation. 4.3. Specifications for the Building Blocks. 4.4. Design of the Building Blocks. 4.5. Layout and Prototyping. 4.6. Experimental Results. 4.7. Performance Summary. 4.8. Performance Comparison with the State of the Art. 4.9. Summary. CHAPTER 5 - A SD Modulator with Programmable Signal Gain for Automotive Sensor Interfaces. 5.1. Basic Design Considerations. 5.2. Architecture Selection and High-Level Sizing. 5.3. Design of the Building Blocks. 5.4. Layout and Prototyping. 5.5. Experimental Results. 5.6. Summary. APPENDIX A - An Expandible Family of Cascade SD Modulators. A.1. Topology Description. A.2. Non-Ideal Performance. APPENDIX B - Power Estimator for Cascade SD Modulators. B.1. Dominant Error Mechanisms. B.2. Estimation of Power Consumption. References.

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