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Esd: Design and Synthesis
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Table of Contents

About the Author. Preface. Acknowledgements. 1 ESD Design Synthesis. 1.1 ESD Design Synthesis and Architecture Flow. 1.2 ESD Design - The Signal Path and the Alternate Current Path. 1.3 ESD Electrical Circuit and Schematic Architecture Concepts. 1.4 Mapping Semiconductor Chips and ESD Design. 1.5 ESD Chip Architecture and ESD Test Standards. 1.6 ESD Testing. 1.7 ESD Chip Architecture and ESD Alternative Current Path. 1.8 ESD Networks, Sequencing and Chip Architecture. 1.9 ESD Design Synthesis - Latchup-Free ESD Networks. 1.10 ESD Design Concepts - Buffering - Inter-Device. 1.11 ESD Design Concepts - Ballasting - Inter-Device. 1.12 ESD Design Concepts - Ballasting - Intra-Device. 1.13 ESD Design Concepts - Distributed Load Techniques. 1.14 ESD Design Concepts - Dummy Circuits. 1.15 ESD Design Concepts - Power Supply De-coupling. 1.16 ESD Design Concepts - Feedback Loop De-Coupling. 1.17 ESD Layout and Floorplan-Related Concepts. 1.18 ESD Design Concepts - Analog Circuit Techniques. 1.19 ESD Design Concepts - Wire Bonds. 1.20 Design Rules. 1.21 Summary and Closing Comments. Problems. References. 2 ESD Architecture and Floorplanning. 2.1 ESD Design Floorplan. 2.2 Peripheral I/O Design. 2.3 Lumped ESD Power Clamp in Peripheral I/O Design Architecture. 2.4 Lumped ESD Power Clamp in Peripheral I/O Design Architecture Master/Slave ESD Power Clamp System. 2.5 Array I/O. 2.6 ESD Architecture - Dummy Bus Architecture. 2.7 Native Voltage Power Supply Architecture. 2.8 Mixed-Voltage Architecture. 2.9 Mixed-Signal Architecture. 2.10 Mixed-System Architecture - Digital and Analog CMOS. 2.11 Mixed-Signal Architecture - Digital, Analog, and RF Architecture. 2.12 Summary and Closing Comments. Problems. References. 3 ESD Power Grid Design. 3.1 ESD Power Grid. 3.2 Semiconductor Chip Impedance. 3.3 Interconnect Failure and Dynamic On-Resistance. 3.4 Interconnect Wire and Via Guidelines. 3.5 ESD Power Grid Resistance. 3.6 Power Grid Layout Design. 3.7 ESD Specification Power Grid Considerations. 3.8 Power Grid Design Synthesis - ESD Design Rule Checking Methods. 3.9 Summary and Closing Comments. Problems. References. 4 ESD Power Clamp. 4.1 ESD Power Clamps. 4.2 Design Synthesis of ESD Power Clamps. 4.3 Design Synthesis of ESD Power Clamps - The ESD Power Clamp Shunting Element. 4.4 ESD Power Clamp Issues. 4.5 ESD Power Clamp Design. 4.6 ESD Power Clamp Design Synthesis - Bipolar ESD Power Clamps. 4.7 Master/Slave ESD Power Clamp Systems. 4.8 Summary and Closing Comments. Problems. References. 5 ESD Signal Pin Network Design and Synthesis. 5.1 ESD Signal Pin Structures. 5.2 ESD Signal Input Structures - ESD and Bond Pads Layout. 5.3 ESD Design Synthesis and Layout of MOSFETs. 5.4 ESD Design Synthesis and Layout of Diodes. 5.5 ESD Design Synthesis of SCRs. 5.6 ESD Design Synthesis and Layout of Resistors. 5.7 ESD Design Synthesis of Inductors. 5.8 Summary and Closing Comments. Problems. References. 6 Guard Ring Design and Synthesis. 6.1 Guard Ring Design and Integration. 6.2 Guard Ring Characterization. 6.3 Semiconductor Chip Guard Ring Seal. 6.4 I/O to Core Guard Rings. 6.5 I/O to I/O Guard Rings. 6.6 Within I/O Guard Rings. 6.7 ESD Signal Pin Guard Rings. 6.8 Library Element Guard Rings. 6.9 Mixed-Signal Guard Rings - Digital to Analog. 6.10 Mixed-Voltage Guard Rings - High Voltage to Low Voltage. 6.11 Passive and Active Guard Rings. 6.12 Trench Guard Rings. 6.13 TSV Guard Rings 6.14 Guard Ring DRC. 6.15 Guard Ring and Computer Aided Design Methods. 6.16 Summary and Closing Comments. Problems. References. 7 ESD Full-Chip Design Integration and Architecture. 7.1 Design Synthesis and Integration. 7.2 Digital Design. 7.3 Custom Design vs. Standard Cell Design. 7.4 Memory ESD Design. 7.5 Microprocessor ESD Design. 7.6 Application-Specific Integrated Circuits. 7.7 CMOS Image Processing Chip Design. 7.8 Mixed-Signal Architecture. 7.9 Summary and Closing Comments. Problems. References. Index.

About the Author

Dr. Steven H. Voldman, IEEE Fellow, Vermont, USA Prolific Wiley writer, Dr. Steven Voldman has been involved with ESD work since 1991. He has been Chairman of the ESD Association WG 5.5 on TLP testing since 2001 and he was Chairman of the SEMATECH ESD Working Group on ESD Technology from 1995 until 1998. Dr. Voldman worked 25 years at IBM before working at Qimonda in 2007 and then TSMC Corporation in 2008. Currently he holds 181 patents in the areas of ESD and latchup, and has 125 pending. His fields of expertise are electrostatic discharge (ESD) protection, latchup, ESD testing and ESD design. To date he has worked on many design architectures from SRAM, DRAM, ASICs, Microprocessors, NVRAMs, image processing designs and power technology.

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