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Formal Verification


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Intel insiders demystify formal verification to improve circuit design and increase productivity

Table of Contents

Formal Verification: From Dreams to Reality Basic Formal Verification Algorithms Introduction to SystemVerilog Assertions Formal Property Verification Effective FPV For Design Exercise Effective FPV for Verification FPV "Apps" for Specific SOC Problems Formal Equivalence Verification Formal Verification's Greatest Bloopers: The Danger of False Positives Dealing with Complexity Your New FV-Aware Lifestyle

About the Author

Erik has worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. Currently he works in the Design Technology and Solutions division, where he supports formal verification usage for Intel teams worldwide. In his spare time he hosts the "Math Mutation" podcast, and serves as an elected director on the Hillsboro school board. Tom recently joined the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis. Kiran has been working at intel India for past 11 years and has worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of verification including formal verification. Currently he leads the formal verification efforts for the graphics design in Visual Platform Group and supports formal verification at intel india site.


"...the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation...I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification..."

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