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High Performance Embedded Computing Handbook
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Over the past several decades, applications permeated by advances in digital signal processing have undergone unprecedented growth in capabilities. The editors and authors of High Performance Embedded Computing Handbook: A Systems Perspective have been significant contributors to this field, and the principles and techniques presented in the handbook are reinforced by examples drawn from their work. The chapters cover system components found in today's HPEC systems by addressing design trade-offs, implementation options, and techniques of the trade, then solidifying the concepts with specific HPEC system examples. This approach provides a more valuable learning tool, Because readers learn about these subject areas through factual implementation cases drawn from the contributing authors' own experiences. Discussions include: Key subsystems and components Computational characteristics of high performance embedded algorithms and applications Front-end real-time processor technologies such as analog-to-digital conversion, application-specific integrated circuits, field programmable gate arrays, and intellectual property--based design Programmable HPEC systems technology, including interconnection fabrics, parallel and distributed processing, performance metrics and software architecture, and automatic code parallelization and optimization Examples of complex HPEC systems representative of actual prototype developments Application examples, including radar, communications, electro-optical, and sonar applications The handbook is organized around a canonical framework that helps readers navigate through the chapters, and it concludes with a discussion of future trends in HPEC systems. The material is covered at a level suitable for practicing engineers and HPEC computational practitioners and is easily adaptable to their own implementation requirements.
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Table of Contents

INTRODUCTION A Retrospective on High Performance Embedded Computing D.R. Martinez HPEC Hardware Systems and Software Technologies HPEC Multiprocessor System Representative Example of a High Performance Embedded Computing System D.R. Martinez System Complexity Implementation Techniques Software Complexity and System Integration System Architecture of a Multiprocessor System D.R. Martinez A Generic Multiprocessor System A High Performance Hardware System Custom VLSI Implementation: Custom VLSI Hardware A High Performance COTS Programmable Signal Processor High Performance Embedded Computers: Development Process and Management Perspectives D.R. Martinez Development Process Case Study: Airborne Radar HPEC System: Programmable Signal Processor Development; Software Estimation, Monitoring, and Configuration Control; PSP Software Integration, Optimization, and Verification Trends Computational Nature of High Performance Embedded Systems Computational Characteristics of High Performance Embedded Algorithms and Applications M. Arakawa and R.A. Bond General Computational Characteristics of HPEC Complexity of HPEC Algorithms Parallelism in HPEC Algorithms and Architectures Future Trends Radar Signal Processing: An Example of High Performance Embedded Computing R.A. Bond and A.I. Reuther A Canonical HPEC Radar Algorithm: Subband Analysis and Synthesis; Adaptive Beamforming; Pulse Compression; Doppler Filtering; Space-Time Adaptive Processing; Subband Synthesis Revisited; CFAR Detection Example Architecture of the Front-End Processor: A Discussion of the Back-End Processing Front-End Real-Time Processor Technologies Analog-to-Digital Conversion J.C. Anderson and H.H. Kim Conceptual ADC Operation Static Metrics:Offset Error; Gain Error; Differential Nonlinearity; Integral Nonlinearity Dynamic Metrics: Resolution; Monotonicity; Equivalent Input-Referred Noise (Thermal Noise); Quantization Error; Ratio of Signal to Noise and Distortion; Effective Number of Bits; Spurious-Free Dynamic Range; Dither; Aperture Uncertainty System-Level Performance Trends and Limitations: Trends in Resolution; Trends in Effective Number of Bits; Trends in Spurious-Free Dynamic Range; Trends in Power Consumption; ADC Impact on Processing Gain High-Speed ADC Design: Flash ADC; Architectural Techniques for Power Saving; Pipeline ADC Power Dissipation Issues in High-Speed ADCs Implementation Approaches of Front-End Processors M.M. Vai and H.T. Nguyen Front-End Processor Design Methodology Front-End Signal Processing Technologies: Full-Custom ASIC; Synthesized ASIC; FPGA Technology; Structured ASIC Intellectual Property Development Cost Design Space Design Case Studies: Channelized Adaptive Beamformer Processor; Radar Pulse Compression Processor; Co-design Benefits Application-Specific Integrated Circuits M.M. Vai, W.S. Song, and B.M. Tyrell Integrated Circuit Technology Evolution CMOS Technology: MOSFET CMOS Logic Structures: Static Logic; Dynamic CMOS Logic Integrated Circuit Fabrication Performance Metrics: Speed; Power Dissipation Design Methodology: Full-Custom Physical Design; Synthesis Process; Physical Verification; Simulation; Design for Manufacturability Packages Testing: Fault Models; Test Generation for Stuck-at Faults; Design for Testability; Built-in Self-Test Case Study Field Programmable Gate Arrays M.Leeser FPGA Structures: Basic Structures Found in FPGAs Modern FPGA Architectures: Embedded Blocks; Future Directions Commercial FPGA Boards and Systems Languages and Tools for Programming FPGAs: Hardware Description Languages; High-Level Languages; Library-Based Solutions Case Study: Radar Processing on an FPGA: Project Description; Parallelism: Fine-Grained versus Coarse-Grained; Data Organization; Experimental Results Challenges to High Performance With FPGA Architectures: Data: Movement and Organization; Design Trade-offs Intellectual Property-Based Design W. Wolf Classes of Intellectual Property Sources of Intellectual Property Licenses for Intellectual Property CPU Cores Busses I/O Devices Memories Operating Systems Software Libraries and Middleware IP-Based Design Methodologies Standards-Based Design Systolic Array Processors M.M. Vai, H.T. Nguyen, P.A. Jackson, and W.S. Song Beamforming Processor Design Systolic Array Design Approach Design Examples: QR Decomposition Processor; Real-Time FFT Processor; Bit-Level Systolic Array Methodology Programmable High Performance Embedded Computing Systems Computing Devices K. Teitelbaum Common Metrics: Assessing the Required Computation Rate; Quantifying the Performance of COTS Computing Devices Current COTS Computing Devices in Embedded Systems: General-Purpose Microprocessors: Word Length, Vector Processing Units, Power Consumption versus Performance, Memory Hierarchy, Some Benchmark Results, Input/Output, Digital Signal Processors; Future Trends: Technology Projections and Extrapolating Current Architectures; Advanced Architectures and the Exploitation of Moore's Law: Multiple-Core Processors, The IBM Cell Broadband Engine, SIMD Processor Arrays, DARPA Polymorphic Computing Architectures, Graphical Processing Units as Numerical Co-processors, FPGA-Based Co-processors Interconnection Fabrics K. Teitelbaum Introduction: Anatomy of a Typical Interconnection Fabric; Network Topology and Bisection Bandwidth; Total Exchange; Parallel Two-Dimensional Fast Fourier Transform-A Simple Example Crossbar Tree Networks: Network Formulas; Scalability of Network Bisection Width; Units of Replication; Pruning Crossbar Tree Networks VXS: A Commercial Example: Link Essentials; VXS-Supported Topologies Performance Metrics and Software Architecture J. Kepner, T. Meuse, and G.E. Schrader Synthetic Aperture Radar Example Application: Operating Modes; Computational Workload Degrees of Parallelism: Parallel Performance Metrics (no communication); Parallel Performance Metrics (with communication); Amdahl's Law Standard Programmable Multi-Computer: Network Model Parallel Programming Models and Their Impact: High-Level Programming Environment with Global Arrays System Metrics: Performance; Form Factor; Efficiency; Software Cost Appendices: A Synthetic Aperture Radar Algorithm: Scalable Data Generator; Stage 1: Front-End Sensor Processing; Stage 2: Back-End Knowledge Formation Programming Languages J.M. Lebak Principles of Programming Embedded Signal Processing Systems Evolution of Programming Languages Features of Third-Generation Programming Languages: Object-Oriented Programming; Exception Handling; Generic Programming Use of Specific Languages in High Performance Embedded Computing: C; Fortran; Ada; C++; Java Future Development of Programming Languages Summary: Features of Current Programming Languages Portable Software Technology J.M. Lebak Libraries: Distributed and Parallel Programming; Surveying the State of Portable Software Technology: Portable Math Libraries, Portable Performance Using Math Libraries; Parallel and Distributed Libraries; Example: Expression Template Use in the MIT Lincoln Laboratory Parallel Vector Library Parallel and Distributed Processing A. I. Reuther and H. G. Kim Parallel Programming Models: Threads: Pthreads, OpenMP; Message Passing: Parallel Virtual Machine, Message Passing Interface; Partitioned Global Address Space: Unified Parallel C, VSIPL++; Applications: Fast Fourier Transform, Synthetic Aperture Radar Distributed Computing Models: Client-Server: SOAP, Java Remote Method Invocation, Common Object Request Broker Architecture; Data Driven: Java Messaging Service, Data Distribution Service; Applications: Radar Open Systems Architecture, Integrated Sensing and Decision Support Automatic Code Parallelization and Optimization N.T. Bliss Instruction-Level Parallelism versus Explicit-Program Parallelism Automatic Parallelization Approaches: A Taxonomy Maps and Map Independence Local Optimization in an Automatically Tuned Library Compiler and Language Approach Dynamic Code Analysis in a Middleware System High Performance Embedded Computing Application Examples Radar Applications K. Teitelbaum Basic Radar Concepts:Pulse-Doppler Radar Operation; Multichannel Pulse-Doppler; Adaptive Beamforming; Space-Time Adaptive Processing Mapping Radar Algorithms onto HPEC Architectures: Round-Robin Partitioning; Functional Pipelining; Coarse-Grain Data-Parallel Partitioning; Fine-Grain Data-Parallel Partitioning Implementation Examples: Radar Surveillance Processor; Adaptive Processor (Generation 1); Adaptive Processor (Generation 2); KASSPER A Sonar Application W.R. Bernecky Sonar Problem Description Designing an Embedded Sonar System: The Sonar Processing Thread; Prototype Development; Computational Requirements; Parallelism; Implementing the Real-Time System; Verify Real-Time Performance; Verify Correct Output An Example Development: System Attributes; Sonar Processing Thread Computational Requirements; Sensor Data Collection; Two-Dimensional Fast Fourier Transform; Covariance Matrix Formation; Covariance Matrix Inversion; Adaptive Beamforming; Broadband Formation; Normalization; Detection; Display Preparation and Operator Controls; Summary of Computational Requirements; Parallelism Hardware Architecture Software Considerations Embedded Sonar Systems of the Future References Communications Applications J.I. Goodman and T.G. Macdonald Communications Application Challenges Communications Signal Processing, Transmitter Signal Processing; Transmitter Processing Requirements; Receiver Signal Processing; Receiver Processing Requirements Development of a Real-Time Electro-Optical Reconnaissance System R.A. Coury Aerial Surveillance Background Methodology: Performance Modeling; Feature Tracking and Optic Flow; Three-Dimensional Site Model Generation; Challenges; Camera Model; Distortion System Design Considerations: Altitude; Sensor; GPS/IMU; Processing and Storage; Communications; Cost; Test Platform Transition to Target Platform: Payload; GPS/IMU; Sensor; Processing; Communications and Storage; Altitude Future Trends Application and HPEC System Trends D.R. Martinez Introduction: Sensor Node Architecture Trends Hardware Trends Software Trends Distributed Net-Centric Architecture A Review on Probabilistic CMOS (PCMOS) Technology: From Device Characteristics to Ultra-Low-Energy SOC Architectures K.V. Palem, L.N. Chakrapani, B.E.S. Akgul, and P. Korkmaz Characterizing the Behavior of a PCMOS Switch: Inverter Realization of a Probabilistic Switch; Analytical Model and the Three Laws of a PCMOS Inverter; Realizing a Probabilistic Inverter with Limited Available Noise Realizing PCMOS-Based Low-Energy Architectures: Metrics for Evaluating PCMOS-Based Architectures; Experimental Methodology; Metrics for Analysis of PCMOS-Based Implementations; Hyperencryption Application and PCMOS-Based Implementation; Results and Analysis; PCMOS-Based Architectures for Error-Tolerant Applications Advanced Microprocessor Architectures J. McMahon, S. Crago, and D. Yeung Background: Established Instruction-Level Parallelism Techniques; Parallel Architectures Motivation for New Architectures: Limitations of Conventional Microprocessors Current Research Microprocessors: Instruction-Level Parallelism: Tile-Based Organization; Explicit Parallelism Model; Scalable On-Chip Networks; Data-Level Parallelism: SIMD Architectures; Vector Architectures; Streaming Architectures; Thread-Level Parallelism: Multithreading and Granularity; Multilevel Memory; Speculative Execution Real-Time Embedded Applications: Scalability; Input/Output Bandwidth; Programming Models and Algorithm Mapping Glossary of Acronyms and Abbreviations Index

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