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Structured Computer Organization, specifically written for undergraduate students, is a best-selling guide that provides an accessible introduction to computer hardware and architecture. This text will also serve as a useful resource for all computer professionals and engineers who need an overview or introduction to computer architecture. This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture. Tanenbaum's renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the author's popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity.
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Table of Contents

CHAPTER 1 INTRODUCTION1.1 STRUCTURED COMPUTER ORGANIZATION1.1.1 Languages, Levels, and Virtual Machines1.1.2 Contemporary Multilevel Machines1.1.3 Evolution of Multilevel Machines1.2 MILESTONES IN COMPUTER ARCHITECTURE1.2.1 The Zeroth Generation (Mechanical Computers (1642-1945))1.2.2 The First Generation (Vacuum Tubes (1945-1955))1.2.3 The Second Generation (Transistors (1955-1965))1.2.4 The Third Generation (Integrated Circuits (1965-1980))1.2.5 The Fourth Generation (Very Large Scale Integration (1980-?))1.2.6 The Fifth Generation (Low-Power and Invisible Computers)1.3 THE COMPUTER ZOO1.3.1 Technological and Economic Forces1.3.2 The Computer Spectrum1.3.3 Disposable Computers1.3.4 Microcontrollers1.3.5 Mobile and Game Computers1.3.6 Personal Computers1.3.7 Servers1.3.8 Mainframes1.4 EXAMPLE COMPUTER FAMILIES1.4.1 Introduction to the x86 Architecture1.4.2 Introduction to the ARM Architecture1.4.3 Introduction to the AVR Architecture1.5 METRIC UNITS1.6 OUTLINE OF THIS BOOKCHAPTER 2 COMPUTER SYSTEMS ORGANIZATION2.1 PROCESSORS2.1.1 CPU Organization2.1.2 Instruction Execution2.1.3 RISC versus CISC2.1.4 Design Principles for Modern Computers2.1.5 Instruction-Level Parallelism2.1.6 Processor-Level Parallelism2.2 PRIMARY MEMORY2.2.1 Bits2.2.2 Memory Addresses2.2.3 Byte Ordering2.2.4 Error-Correcting Codes2.2.5 Cache Memory2.2.6 Memory Packaging and Types2.3 SECONDARY MEMORY2.3.1 Memory Hierarchies2.3.2 Magnetic Disks2.3.3 IDE Disks2.3.4 SCSI Disks2.3.5 RAID2.3.6 Solid-State Disks2.3.7 CD-ROMs2.3.8 CD-Recordables2.3.9 CD-Rewritables2.3.10 DVD2.3.11 Blu-ray2.4 INPUT/OUTPUT2.4.1 Buses2.4.2 Terminals2.4.3 Mice2.4.4 Game Controllers2.4.5 Printers2.4.6 Telecommunications Equipment2.4.7 Digital Cameras2.4.8 Character Codes2.5 SUMMARYCHAPTER 3 THE DIGITAL LOGIC LEVEL3.1 GATES AND BOOLEAN ALGEBRA3.1.1 Gates3.1.2 Boolean Algebra3.1.3 Implementation of Boolean Functions3.1.4 Circuit Equivalence3.2 BASIC DIGITAL LOGIC CIRCUITS3.2.1 Integrated Circuits3.2.2 Combinational Circuits3.2.3 Arithmetic Circuits3.2.4 Clocks3.3 MEMORY3.3.1 Latches3.3.2 Flip-Flops3.3.3 Registers3.3.4 Memory Organization3.3.5 Memory Chips3.3.6 RAMs and ROMs3.4 CPU CHIPS AND BUSES3.4.1 CPU Chips3.4.2 Computer Buses3.4.3 Bus Width3.4.4 Bus Clocking3.4.5 Bus Arbitration3.4.6 Bus Operations3.5 EXAMPLE CPU CHIPS3.5.1 The Intel Core i73.5.2 The Texas Instruments OMAP4430 System-on-a-Chip3.5.3 The Atmel ATmega168 Microcontroller3.6 EXAMPLE BUSES3.6.1 The PCI Bus3.6.2 PCI Express3.6.3 The Universal Serial Bus3.7 INTERFACING3.7.1 I/O Interfaces3.7.2 Address Decoding3.8 SUMMARYCHAPTER 4 THE MICROARCHITECTURE LEVEL4.1 AN EXAMPLE MICROARCHITECTURE4.1.1 The Data Path4.1.2 Microinstructions4.1.3 Microinstruction Control: The Mic-14.2 AN EXAMPLE ISA: IJVM4.2.1 Stacks4.2.2 The IJVM Memory Model4.2.3 The IJVM Instruction Set4.2.4 Compiling Java to IJVM4.3 AN EXAMPLE IMPLEMENTATION4.3.1 Microinstructions and Notation4.3.2 Implementation of IJVM Using the Mic-14.4 DESIGN OF THE MICROARCHITECTURE LEVEL4.4.1 Speed versus Cost4.4.2 Reducing the Execution Path Length4.4.3 A Design with Prefetching: The Mic-24.4.4 A Pipelined Design: The Mic-34.4.5 A Seven-Stage Pipeline: The Mic-44.5 IMPROVING PERFORMANCE4.5.1 Cache Memory4.5.2 Branch Prediction4.5.3 Out-of-Order Execution and Register Renaming4.5.4 Speculative Execution4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL4.6.1 The Microarchitecture of the Core i7 CPU4.6.2 The Microarchitecture of the OMAP4430 CPU4.6.3 The Microarchitecture of the ATmega168 Microcontroller4.7 COMPARISON OF THE CORE I7, OMAP4430, AND ATMEGA1684.8 SUMMARYCHAPTER 5 THE INSTRUCTION SET ARCHITECTURE LEVEL5.1 OVERVIEW OF THE ISA LEVEL5.1.1 Properties of the ISA Level5.1.2 Memory Models5.1.3 Registers5.1.4 Instructions5.1.5 Overview of the ARM ISA Level5.1.6 Overview of the x86 ISA Level5.1.7 Overview of the AVR Level5.2 DATA TYPES5.2.1 Numeric Data Types5.2.2 Nonnumeric Data Types5.2.3 Data Types on the ARM5.2.4 Data Types on the x865.2.5 Data Types on the AVR5.3 INSTRUCTION FORMATS5.3.1 Design Criteria for Instruction Formats5.3.2 Expanding Opcodes5.3.3 The ARM Instruction Formats5.3.4 The x86 Instruction Formats5.3.5 The AVR Instruction Formats5.4 ADDRESSING 3605.4.1 Addressing Modes5.4.2 Immediate Addressing5.4.3 Direct Addressing5.4.4 Register Addressing5.4.5 Register Indirect Addressing5.4.6 Indexed Addressing5.4.7 Based-Indexed Addressing5.4.8 Stack Addressing5.4.9 Addressing Modes for Branch Instructions5.4.10 Orthogonality of Opcodes and Addressing Modes5.4.11 The ARM Addressing Modes5.4.12 The x86 Addressing Modes5.4.13 The AVR Addressing Modes5.4.14 Discussion of Addressing Modes5.5 INSTRUCTION TYPES5.5.1 Data Movement Instructions5.5.2 Dyadic Operations5.5.3 Monadic Operations5.5.4 Comparisons and Conditional Branches5.5.5 Procedure Call Instructions5.5.6 Loop Control5.5.7 Input/Output5.5.8 The ARM Instructions5.5.9 The x86 Instructions5.5.10 The AVR Instructions5.5.11 Comparison of Instruction Sets5.6 FLOW OF CONTROL5.6.1 Sequential Flow of Control and Branches5.6.2 Procedures5.6.3 Coroutines and Threads5.6.5 Traps5.6.5 Interrupts5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI5.7.1 The Towers of Hanoi in ARM Assembly Language5.7.2 The Towers of Hanoi in x86 Assembly Language5.8 THE NVIDIA Fermi Architecture5.8.1 The Problem with the ARM and x86 Architectures5.8.2 The Fermi Model: Massively Data-Parallel Computing5.8.3 Regularizing Memory References5.8.4 Thread Scheduling5.8.5 Reducing Branch Divergence5.9 SUMMARYCHAPTER 6 THE OPERATING SYSTEM MACHINE LEVEL6.1 VIRTUAL MEMORY6.1.1 Paging6.1.2 Implementation of Paging6.1.3 Demand Paging and the Working Set Model6.1.4 Page Replacement Policy6.1.5 Page Size and Fragmentation6.1.6 Segmentation6.1.7 Implementation of Segmentation6.1.8 Virtual Memory on the ARM6.1.9 Virtual Memory on the x866.1.10 Virtual Memory and Caching6.2 VIRTUALIZATION6.2.1 Why direct I/O hampers system design6.2.2 Implementation of Virtual I/O access6.2.3 Support for Virtualized I/O and Paging6.2.4 IVT Virtualization in the x86 architecture6.3 SUPPORT FOR PARALLEL PROCESSING6.3.1 Process and Thread Creation6.3.2 Race Conditions6.3.3 Process Synchronization Using Semaphores and Barriers6.4 EXAMPLE OPERATING SYSTEMS6.4.1 Introduction6.4.2 Examples of Virtual Memory6.4.3 Examples of Virtualization6.4.4 Examples of Process and Thread Management6.5 SUMMARYCHAPTER 7 THE ASSEMBLY LANGUAGE LEVEL7.1 INTRODUCTION TO ASSEMBLY LANGUAGE7.1.1 What Is an Assembly Language?7.1.2 Why Use Assembly Language?7.1.3 Format of an Assembly Language Statement7.1.4 Pseudoinstructions7.2 MACROS7.2.1 Macro Definition, Call, and Expansion7.2.2 Macros with Parameters7.2.3 Advanced Features7.2.4 Implementation of a Macro Facility in an Assembler7.3 THE ASSEMBLY PROCESS7.3.1 Two-Pass Assemblers7.3.2 Pass One7.3.3 Pass Two7.3.4 The Symbol Table7.4 LINKING AND LOADING7.4.1 Tasks Performed by the Linker7.4.2 Structure of an Object Module7.4.3 Binding Time and Dynamic Relocation7.4.4 Dynamic Linking7.5 SUMMARYCHAPTER 8 PARALLEL COMPUTER ARCHITECTURES8.1 ON-CHIP PARALELLISM8.1.1 Instruction-Level Parallelism8.1.2 On-Chip Multithreading8.1.3 Single-Chip Multiprocessors8.2 Systems on a Chip (SoCs)8.2.1 Network Processors8.2.2 Media Processors8.2.3 Cryptoprocessors8.3 SHARED-MEMORY MULTIPROCESSORS8.3.1 Multiprocessors vs. Multicomputers8.3.2 Memory Semantics8.3.3 UMA Symmetric Multiprocessor Architectures8.3.4 NUMA Multiprocessors8.3.5 COMA Multiprocessors8.4 MESSAGE-PASSING MULTICOMPUTERS8.4.1 Interconnection Networks8.4.2 MPPs--Massively Parallel Processors8.4.3 Cluster Computing8.4.4 Communication Software for Multicomputers8.4.5 Scheduling8.4.6 Application-Level Shared Memory8.4.7 Performance8.5 GRID COMPUTING8.6 SUMMARYCHAPTER 9 READING LIST AND BIBLIOGRAPHY9.1 SUGGESTIONS FOR FURTHER READING9.2 ALPHABETICAL BIBLIOGRAPHY

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