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The VLSI Handbook, Second Edition

New or Used: $549.09
For the new millenium, Wai-Kai Chen introduced a monumental reference for the design, analysis, and prediction of VLSI circuits: The VLSI Handbook. Still a valuable tool for dealing with the most dynamic field in engineering, this second edition includes 13 sections comprising nearly 100 chapters focused on the key concepts, models, and equations. Written by a stellar international panel of expert contributors, this handbook is a reliable, comprehensive resource for real answers to practical problems. It emphasizes fundamental theory underlying professional applications and also reflects key areas of industrial and research focus. WHAT'S IN THE SECOND EDITION? Sections on! Low-power electronics and design VLSI signal processing Chapters on! CMOS fabrication Content-addressable memory Compound semiconductor RF circuits High-speed circuit design principles SiGe HBT technology Bipolar junction transistor amplifiers Performance modeling and analysis using SystemC Design languages, expanded from two chapters to twelve Testing of digital systems Structured for convenient navigation and loaded with practical solutions, The VLSI Handbook, Second Edition remains the first choice for answers to the problems and challenges faced daily in engineering practice.
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Table of Contents

VLSI TECHNOLOGYBipolar Technology; B. Gunnar Malm, Jan V. Grahn and Mikael OEstlingCMOS/BiCMOS Technology; Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi and Hiroshi IwaiSilicon-On-Insulator Technology; Sorin CristoloveanuSiGe HBT Technology; John D. CresslerSilicon Carbide Technology; Philip G. NeudeckPassive Components; Ashraf LotfiPower IC Technologies; Akio NakagawaMicroelectronics Packaging; Bi-Shiou ChiouMultichip Module Technologies; Victor Boyadzhyan andJohn Choma, Jr.DEVICES AND THEIR MODELSBipolar Junction Transistor Circuits; David J. Comer and Donald T. ComerRF Passive IC Components; Thomas H. Lee, Maria del Mar Hershenson, Sunderarajan S. Mohan, Kirad Samavati and C. Patrick YueCMOS Fabrication; Jeff JessingAnalog Circuit Simulation; J. Gregory RollinsInterconnect Modeling and Simulation; Michel S. Nakhla and Ramachandra AcharLOW POWER ELECTRONICS AND DESIGNSystem-Level Power Management: An Overview; Ali Iranli and Massoud PedramCommunication-Based Design for Nanoscale SoCs; Umit Y. Ogras and Radu MarculescuPower-Aware Architectural Synthesis; Robert P. Dick, Li Shang and Niraj K. JhaDynamic Voltage Scaling for Low-Power Hard Real-Time Systems; Jihong Kim, Flavius Gruian and Dongkun ShinLow-Power Microarchitecture Techniques and Compiler Design Techniques; Emil Talpes and Diana MarculescuArchitecture and Design Flow Optimizations for Power-Aware FPGAs; Aman Gayasen and Narayanan VijaykrishnanTechnology Scaling and Low-Power Circuit Design; Ali KeshavarziAMPLIFIERSCMOS Amplifier Design; Harry W. Li, R. Jacob Baker and Donald C. ThelenBipolar Junction Transistor Amplifiers; David J. Comer and Donald T. ComerHigh-Frequency Amplifiers; Chris Toumazou and Alison BurdettOperational Transconductance Amplifiers; Mohammed Ismail, Seok-Bae Park, Ayman A. Fayed and R.F. WassenaarLOGIC CIRCUITSExpressions of Logic Functions; Saburo MurogaBasic Theory of Logic Functions; Saburo MurogaSimplification of Logic Expressions; Saburo MurogaBinary Decision Diagrams; Shin-ichi Minato and Saburo MurogaLogic Synthesis with AND and OR Gates in Two Levels; Saburo MurogaSequential Networks; Saburo MurogaLogic Synthesis with AND and OR Gates in Multi-Levels; Yuichi Nakamura and Saburo MurogaLogic Properties of Transistor Circuits; Saburo MurogaLogic Synthesis with NAND (or NOR) Gates in Multi-Levels; Saburo MurogaLogic Synthesis with a Minimum Number of Negative Gates; Saburo MurogaLogic Synthesizer with Optimizations in Two Phases; Ko Yoshikawa and Saburo MurogaLogic Synthesizer by the Transduction Method; Saburo MurogaEmitter-Coupled Logic; Saburo MurogaCMOS; Saburo MurogaPass Transistors; Kazuo Yano and Saburo MurogaAdders; Naofumi Takagi, Haruyuki Tago, Charles R. Baugh and Saburo MurogaMultipliers; Naofumi Takagi, Charles R. Baugh and Saburo MurogaDividers; Naofumi Takagi and Saburo MurogaFull-Custom and Semi-Custom Design; Saburo MurogaProgrammable Logic Devices; Saburo MurogaGate Arrays; Saburo MurogaField-Programmable Gate Arrays; Saburo MurogaCell-Library Design Approach; Saburo MurogaComparison of Different Design Approaches; Saburo MurogaMEMORY, REGISTERS AND SYSTEM TIMINGSystem Timing; Baris Taskin, Ivan S. Kourtev and Eby G. FriedmanROM/PROM/EPROM; Jen-Sheng HwangSRAM; Yuh-Kuang TsengEmbedded Memory; Chung-Yu WuFlash Memories; Rick Shih-Jye Shen, Frank Ruei-Ling Lin, Amy Hsiu-Fen Chou, Evans Ching-Song Yang and Charles Ching-Hsiang HsuDynamic Random Access Memory; Kuo-Hsing ChengContent-Addressable Memory; Chi-Sheng Lin and Bin-Da LiuLow-Power Memory Circuits; Martin MargalaANALOG CIRCUITSNyquist-Rate ADC and DAC; Bang-Sup SongOversampled Analog-to-Digital and Digital-to-Analog Converters; John W. Fattaruso and Louis A. Williams IIIRF Communication Circuits; Michiel Steyaert, Wouter De Cock and Patrick ReynaertPLL Circuits; Muh-Tian Shiue and Chorng-kuang WangSwitched-Capacitor Filters; Andrea BaschirottoMICROPROCESSOR AND ASICTiming and Signal Integrity Analysis; Abhijit Dharchoudhury, David Blaauw and Shantanu GangulyMicroprocessor Design Verification; Vikram IyengarMicroprocessor Layout Method; Tanay KarnikArchitecture; Daniel A. Connors and Wen-mei W. HwuLogic Synthesis for Field Programmable Gate Array (FPGA) Technology; John LockwoodTESTING OF DIGITAL SYSTEMSDesign for Testability and Test Architectures; Dimitri Kagaris, Nick Kanopoulos and Spyros TragoudasAutomatic Test Pattern Generation; Spyros TragoudasBuilt-In Self Test; Dimitri KagarisCOMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT TECHNOLOGYCompound Semiconductor Materials; Stephen I. LongCompound Semiconductor Devices for Analog and Digital Circuits; Donald B. EstreichCompound Semiconductor RF Circuits; Donald B. EstreichHigh-Speed Circuit Design Principles; Stephen I. LongDESIGN AUTOMATIONInternet-Based Micro-Electronic Design Automation (IMEDA) Framework; Moon Jung Chung and Heechul KimSystem-Level Design; Alice C. Parker, Yosef Tirat-Gefen and Suhrid A. WadekarPerformance Modeling and Analysis Using VHDL and SystemC; Robert H. Klenke, Jonathan A. Andrews and James H. AylorEmbedded Computing Systems and Hardware/Software Co-Design; Wayne WolfDesign Automation Technology Roadmap; Donald R. CottrellVLSI SIGNAL PROCESSINGComputer Arithmetic for VLSI Signal Processing; Earl E. Swartzlander Jr.VLSI Architectures for JPEG 2000 EBCOT: Design Techniques and Challenges; Yijun Li and Magdy BayoumiVLSI Architectures for Forward Error-Control Decoders; Arshad Ahmed, Seok-Jun Lee, Mohammad Mansour and Naresh R. ShanbhagAn Exploration of Hardware Architectures for Face Detection; T. Theocharides, C. Nicopoulos, K. Irick, N. Vijaykrishnan and M.J. IrwinMultidimensional Logarithmic Number System; Roberto Muscedere, Vassil S. Dimitrov and Graham A. JullienDESIGN LANGUAGESLanguages for Design and Implementation of Hardware; Zainalabedin NavabiSystem Level Design Languages; Shahrzad Mirkhani and Zainalabedin NavabiRT Level Hardware Description with VHDL; Mahsan Rofouei and Zainalabedin NavabiRegister Transfer Level Hardware Description with Verilog; Zainalabedin NavabiRegister-Transfer Level Hardware Description with SystemC; Shahrzad Mirkhani and Zainalabedin NavabiSystem Verilog; Saeed SafariVHDL-AMS Hardware Description Language; Naghmeh Karimi and Zainalabedin NavabiVerification Languages; Hamid Shojaei and Zainalabedin NavabiASIC and Custom IC Cell Information Representation; Naghmeh Karimi and Zainalabedin NavabiTest Languages; Shahrzad Mirkhani and Zainalabedin NavabiTiming Description Languages; Naghmeh Karimi and Zainalabedin NavabiHDL-Based Tools and Environments; Saeed SafariIndex

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