Wafer Scale Integration
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|Format: ||Paperback, 503 pages, Softcover reprint of Edition|
|Other Information: ||black & white illustrations, bibliography|
|Published In: ||United States, 01 February 2012|
Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.
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Table of Contents
1. Promise and Pitfalls of WSI.- WSI and Common Sense.- Evaluation of the Promise.- References.- 2. Feasibility of Large Area Integrated Circuits.- Motivation for Easily Manufacturable Large Area ICs.- Feasibility of Large Area ICs.- Future Research.- Summary and Conclusions.- References.- 3. Architectural Yield Optimization.- WSI Background.- Fault Modeling.- Architectural Yield Modeling.- Optimizing Redundancy in a B-Tree Design.- Results and Conclusions.- References.- 4. Spare Allocation/Reconfiguration for WSI.- A Survey of Reconfiguration Algorithms.- Spare Allocation with Dedicated Spares.- Integrating Diagnosis and Spare Allocation in Large Memories.- Diagnosis and Repair of Large Programmable Logic Arrays.- Computer-Aided Design for Reconfiguration.- Conclusions.- Acknowledgments.- References.- 5. A WSI Image Processor.- Parallel Computer Vision Requirements.- WASP: A WSI Associative String Processor.- ASP Operational Principles.- ASP Software.- WASP Design Strategy.- ASP Development Program.- ASP Performance Forecasts.- Conclusions.- Acknowledgements.- References.- 6. The 3-D Computer: An Integrated Stack of WSI Wafers.- Three-Dimensional Integration.- Concept of a 3-D Computer.- Architecture of the 3-D Computer.- The Enabling 3-D Technologies.- WSI Circuits.- Description of 3-D Operation.- Summary.- Acknowledgments.- References.- 7. Laser Restructurable Technology and Design.- Methodology.- Laser Restructuring.- Design and Test.- Physical Design and Fabrication.- Applications.- Conclusions.- Acknowledgement.- References.- 8. High Yield In-Situ Fabrication of Multilevel Interconnections for WSI.- Wafer Scale Integration.- Wafer Scale Hybrid Packaging and Its Impact on WSI.- The Wafer Transmission Module.- Organic Insulators.- Whole Wafer Lithography Using Electron Beam Systems.- Planarized Processing.- Parylene and Parylene Derivatives for VDP.- Ionized Cluster Beam (ICB) and Partially Ionized Beam (PIB) Metal Deposition.- ICB of Organics.- Development of a Dry Lift-Off Process.- Single Wafer Processing.- Focused Ion Beam Testing and Repair.- Conclusions.- Acknowledgements.- References.- 9. Wafer-Scale Testing/Design for Testability.- The Problem of Wafer-scale Testing.- Steps in Testing and Configuring a Wafer-scale System.- A Short Review of Testing Methods.- Active Element Testing.- Switch Array Testing.- Conclusions.- Acknowledgement.- References.- 10. Wafer-Scale Multichip Packaging Technology.- Silicon Multichip Packaging.- Innovative Approaches to Chip Mounting and Interconnection.- Packaging the Silicon Wafer.- Summary.- References.
Springer-Verlag New York Inc.|
23.5 x 15.5 x 2.7 centimetres (0.80 kg)|
15+ years |