Introduction.- Overview of ILP Architectures.- Scheduling Basic Blocks.- Trace Scheduling.- Percolation Scheduling.- Modulo Scheduling.- Software Pipelining by Kernal Recognition.- Epilogue.
Alex Aiken is the Alcatel-Lucent Professor and the current
chair of the Computer Science Department at Stanford. His research
interests include most areas of programming languages and compilers
and particularly automated methods of analysis for both high
performance and high reliability.
Utpal Banerjee has a PhD in mathematics from Carnegie-Mellon
University and a PhD in computer science from the University of
Illinois at Urbana-Champaign. He has taught at the University of
Cincinnati, Arizona State University and the University of
Illinois. Dr. Banerjee has served as a research staff member at
Honeywell, Fairchild, Control Data and Intel corporations. His
current affiliation is with the Department of Computer Science,
University of California at Irvine. He has published a number of
papers and books on restructuring compilers, including encyclopedia
articles and a series of books on loop transformations. He is a
fellow of the IEEE and a fellow of the ACM.
Arun Kejariwal is a Statistical Learning Principal at
Machine Zone. He co-founded MZ Research and currently manages a
team of research scientists. He is leading the research and
development of novel algorithms for fraud detection, anomaly
detection in security and operational data. Prior to joining
Machine Zone, he was a lead in the Data Fidelity Team at Twitter
and open sourced standalone R packages for anomaly detection and
breakout detection. He received Ph.D. in Computer Science from UC
Irvine and is a Senior Member of IEEE and ACM.
Alexandru Nicolau’s research is in the areas of Parallel
Processing/ILP, and Embedded Systems/Design Automation. His
interests focus on Computer Performance/power tradeoffs,
parallelizing compilers, GPUs. His current work involves
collaborations both within and outside UCI, most recently with
researchers at Stanford, University of Michigan, UCLA, UCSD as part
of a flagship NSF Expedition project, and a separate grant with
UIUC. He authored over 300 peer-reviewed papers and several books.
He is the Editor-in-Chief of the International Journal of Parallel
Processing, and an IEEE Fellow.
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