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Field-Programmable Gate Arrays
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Table of Contents

Preface.- 1 Introduction to FPGAs.- 1.1 Evolution of Programmable Devices.- 1.2 What is an FPGA?.- 1.3 Economics of FPGAs.- 1.4 Applications of FPGAs.- 1.5 Implementation Process.- 1.6 Concluding Remarks.- 2 Commercially Available FPGAs.- 2.1 Programming Technologies.- 2.2 Commercially Available FPGAs.- 2.3 FPGA Design Flow Example.- 2.4 Concluding Remarks.- 3 Technology Mapping for FPGAs.- 3.1 Logic Synthesis.- 3.2 Lookup Table Technology Mapping.- 3.3 Multiplexer Technology Mapping.- 3.4 Final Remarks.- 4 Logic Block Architecture.- 4.1 Logic Block Functionality versus Area-Efficiency.- 4.2 Impact of Logic Block Functionality on FPGA Performance.- 4.3 Final Remarks and Future Issues.- 5 Routing for FPGAs.- 5.1 Routing Terminology.- 5.2 General Strategy for Routing in FPGAs.- 5.3 Routing for Row-Based FPGAs.- 5.4 Routing for Symmetrical FPGAs.- 6 Flexibility of FPGA Routing Architectures.- 6.1 FPGA Architectural Assumptions.- 6.2 Experimental Procedure.- 6.3 Limitations of the Study.- 6.4 Experimental Results.- 6.5 Conclusions.- 7 A Theoretical Model for FPGA Routing.- 7.1 Architectural Assumptions for the FPGA.- 7.2 Overview of the Stochastic Model.- 7.3 Previous Research for Predicting Channel Densities.- 7.4 The Probability of Successfully Routing a Connection.- 7.5 Using the Stochastic Model to Predict Routability.- 7.6 Final Remarks.- References.

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