1 Introduction.- 2 Netlist and System Partitioning.- 3 Chip Planning.- 4 Global and Detailed Placement.- 5 Global Routing.- 6 Detailed Routing.- 7 Specialized Routing.- 8 Timing Closure. A Solutions to Chapter Exercises.- B Example CMOS Cell Layouts.
Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006).
Jens Lienig is Professor of Electrical Engineering at TU Dresden. He is also the director of the Institute of Electromechanical and Electronic Design at TUD. He has worked as project manager at Tanner Research, Inc. (1996-1999) and Robert Bosch GmbH (1999-2002).
Igor L. Markov is a Fellow of IEEE and an ACM Distinguished Scientist. In addition to his career as a Professor of Electrical Engineering and Computer Science at the University of Michigan, he has worked at Google (2014-2017) and has been with Facebook since 2018.
Jin Hu was a PhD student at the Computer Science and Engineering (CSE) Division at the University of Michigan. Afterwards, she has been with IBM Corp. (2013-2017), Bloomberg L.P. (2017-2019) and Two Sigma Insurance Quantified (TSIQ) (since 2019).
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