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Design of Cost-efficient Interconnect Processing Units
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Table of Contents

Towards Multicores: Technology and Software Complexity. On-Chip Bus vs Network-on-Chip. NoC Topology. The Spidergon STNoC. SoC and NoC Design Methodology and Tools. Conclusions and Future Work.

About the Author

Marcello Coppola (STMicroelectronics, Grenoble, France) (Author) , Miltos D. Grammatikakis (ISD SA, Heraklion, Greece) (Author) , Riccardo Locatelli (STMicroelectronics, Grenoble Cedex, France) (Author) , Giuseppe Maruccia (STMicroelectronics, Grenoble, France) (Author) , Lorenzo Pieralisi (STMicroelectronics, Grenoble, France) (Author)

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